1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which a substrate having a step is planarized, and to a manufacturing method therefor.
2. Description of the Related Art
As integration of semiconductor devices increases, there is more need for an interconnection for a metallic multilayer. An intermetal dielectric (IMD) for insulating an under layer and an upper layer is very important for forming the multilayer interconnection. This is because planarization of the IMD affects a depth of focus (DOF) of a stepper used for a photolithography process, to thereby lower a total process margin. This problem is also present when planarizing an interlayer dielectric (ILD) layer.
The planarization of the IMD is a very important step when forming a metal interconnection of a DRAM and a merged DRAM logic device (MDL). This is because a complicated three-dimensional memory cell including a transistor and a capacitor is formed in a limited area. In general, to improve a capacitance, the surface area of a storage node of a capacitor is increased by being formed three dimensionally in the limited cell area of the semiconductor device. However, the three-dimensional storage node has a step higher than in the peripheral area, and such a step difference should be planarized in a later IMD forming process.
The IMD is typically planarized by depositing boron phosphor silicate glass (BPSG) and reflowing the deposited BPSG, depositing spin on glass (SOG) and etching the deposited SOG, or performing a chemical mechanical polishing (CMP) process.
The method for planarizing an IMD by depositing and etching SOG is disclosed in U.S. Pat. No. 5,631,197, entitled xe2x80x9cSacrificial Etchback Layer For Improved Spin-On-Glass Planarization,xe2x80x9d May 1997.
In the method, an SOG layer and a sacrificial layer are stacked on a semiconductor substrate, and the stacked layers are planarized by etchback. However, the method still has room for improvement to achieve a global planarization.
To solve the above problems, it is an objective of the present invention to provide a semiconductor device in which global planarization can be easily realized using wet etch, by depositing a SOG layer having a low step on a semiconductor substrate where a step is formed and curing the low-step SOG layer using electron beams (E-beams).
It is another objective of the present invention to provide a method of manufacturing a semiconductor device in which a substrate is planarized.
Accordingly, to achieve the first objective, there is provided a semiconductor device in which a substrate is planarized, including: a cell area having a high step formed on a first portion of a semiconductor substrate; a peripheral area having a lower step formed on a second portion of the semiconductor substrate, a first layer formed on the cell area and the peripheral area; and a second layer having different etch rates in the cell area and peripheral area due to curing performed only in a peripheral area.
Preferably, the first layer is thicker than a step formed between the cell area and the peripheral area, and the second layer formed on the first layer in the peripheral area is cured with electron beams (E-beams).
It is also preferable that the SOG is formed of hydrosilsesquioxane (HSQ), and the second layer is baked.
It is further preferable that the thickness of the second layer is 1000-10000 xc3x85.
To achieve the second objective, there is provided a method of manufacturing a semiconductor device in which a substrate is planarized, including the steps of: forming first and second layers on a semiconductor substrate having a cell area and a peripheral area, forming a step therebetween; curing the second layer in the peripheral area; and etching back the semiconductor substrate after curing.
Preferably, the first layer is an insulating layer formed of one selected from the group consisting of undoped silicate glass (USG), boron phosphorus silicate glass (BPSG), phosphor silicate glass (PSG), boron silicate glass (BSG), SiOF, a nitride layer and inorganic spin on glass (SOG).
Also, the first layer is thicker than the step formed between the cell area and the peripheral area, the SOG is inorganic SOG formed of HSQ, and the thickness of the second layer is 1000-10000 xc3x85.
The baking process is performed at a chamber temperature of 350-500xc2x0 C. Also, the second layer over the cell area is cured by using a light shielding layer pattern of photoresist with an E-beam dose of 2000 xcexcC/cm2 or more, and power of 1 KeV or more. At this time, preferably, the temperature of the semiconductor substrate is 20-500xc2x0 C.